This invention relates to computer systems and, in particular, to processors that execute decimal arithmetic.
Decimal floating-point operations are becoming increasingly important in commercial transactions, resulting in manufacturers adding hardware specifically designed to execute these operations. Decimal fixed-point operations are equally important and are typically executed in a fixed-point unit of a processor. Additional hardware is usually required in the fixed-point unit to facilitate the execution of these decimal fixed-point instructions. This is important real estate (i.e., occupied space) in a processor with the effect that, as area is added to the stack, there is a potential impact on cycle time. Furthermore, the fixed-point unit contains a 64-bit (or 16-digit) dataflow but the operands for these decimal operations can be up to 31 digits long plus a sign digit, resulting in 128-bit operations. Operations with operands longer then 16 digits must be broken up into smaller operations, which adversely impacts performance. What is needed is an improved technique for executing decimal fixed-point instructions.